Ambipolar transport in CVD grown MoSe₂ monolayer using an ionic liquid gel gate dielectric

Molybdenum diselenide (MoSe₂) is an air stable n-type semiconductor transition metal dichalcogenide (TMD). A sheet of Mo atoms sandwiched between atomic sheets of Se forms the primitive two dimensional MoSe₂ monolayer. Within each layer, Se-Mo-Se atoms are covalently bonded, and vertical stacking of monolayers via van de Waals interactions result in macroscopic MoSe₂ crystals that are naturally occurring and commercially available. In the bulk form, MoSe₂ has an indirect band gap of 1.1 eV which transforms to the technologically important direct band gap of 1.55 eV in an atomically thin monolayer.¹ Exfoliation is a common method used to randomly isolate thin films of this material,² however, molecular beam epitaxy (MBE)^3,4 and chemical vapor deposition (CVD),^5–7 are controlled techniques for reproducible fabrication of large area monolayers. Since Se vacancy formation energy is high in MoSe₂ (leading to fewer vacancies and a more intrinsic semiconductor) its Fermi energy lies nearer to the mid-gap which allows for a tunable Schottky barrier (with a metal contact) and makes ambipolar conduction possible.⁸ Ambipolar transport is desirable since the same device can operate in p- and n-FET modes. In addition, since holes and electrons are transported through the device simultaneously, radiative recombination is possible that can extend its use in optoelectronic applications.

In this work we report on the growth of large area high quality monolayer MoSe₂ crystals via CVD, and observe ambipolar transport when characterized as a field effect transistor (FET) using an ionic liquid (IL) gel as the gate dielectric. During the growth, instead of using MoO₃ powder,^5–7 ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas.⁹ In addition, a high specific capacitance (∼7 μF/cm²) IL was used as the gate dielectric to significantly reduce the operating voltage. The ambipolar effect has been observed under diverse conditions, for eg. in exfoliated¹⁰ and CVD^6,11 grown MoSe₂ multilayers with a SiO₂ dielectric, and on MBE grown monolayers with an IL dielectric at low temperatures.⁴ Our device consists of a CVD grown MoSe₂ monolayer with an IL dielectric that exhibits superior performance at room temperature (294 K). The high specific capacitance of the IL permits access to a wider range of electrostatic doping levels at low operating voltages, while retaining the high on/off ratio (for hole and electron transport) necessary for successful implementation in binary based logic circuits. Testing a typical device as an inverter with a resistive load yields a gain of ∼2. In addition, the ambipolar feature observed using identical metal contacts simplifies device fabrication, and makes monolayer MoSe₂ suitable for use in low power complementary transistor switches.

MoSe₂ crystals were grown via atmospheric pressure CVD in a 1 inch quartz tube furnace. In our technique, instead of MoO₃ powder,^5–7 droplets of ammonium heptamolybdate solution were used to ensure better control of the Mo supplying source, and in addition, sodium cholate was utilized as a promoter to enhance the growth of monolayer MoSe₂ over a larger area.⁹ A typical synthesis consisted of microliter droplets of half-saturated ammonium heptamolybdate solution dried onto the corners of a 2 cm × 5 cm Si/SiO₂ growth substrate that had previously been coated with a layer of sodium cholate (1% solution spin coated 4000 rpm for 60 s). The growth substrate was placed in the center of the furnace and heated to 750 °C at a rate of 70 °C/min. A piece of silicon with 200 mg of selenium powder was positioned upstream in the furnace at a distance of 15 cm from the growth substrate, such that its temperature was approximately 220 °C, sufficient for the powder to melt and evaporate slowly. A flow of 500 sccm N₂ and 15 sccm H₂ carried the selenium vapor into the furnace during a 30 min growth period. After growth, the sample was rapidly cooled by cracking open the furnace and sliding it downstream with respect to the 1 in. quartz tube.

Figure 1(a) shows a top view optical microscope image of these crystals, where the even color contrast indicates the uniform thickness and high quality of the material. The Raman spectrum on one such crystal in Figure 1(b) shows the characteristic A_1g and $E2g1$ vibrational modes with intensity ratio of ∼20 as expected for high quality material.⁵ Figures 1(c) and (d) show an atomic force microscope image of the crystal and the height profile along the white line in panel (c) respectively. The measured height is ∼0.8nm, and together with panel (b) demonstrates that the crystal is 1H-MoSe₂ and one monolayer thick. Using poly(methyl methacrylate) (PMMA) and KOH in a wet etch process,¹² these as grown MoSe₂ monolayers were transferred on to pre-patterned Ti/Au electrode Si/SiO₂ substrates and oven dried in air at 70 ^oC. The transferred crystals stick firmly to the SiO₂ surface and did not peel off in a stream of acetone wash cycles.

Figure 2(a) shows a top view optical microscope image of such a pre-patterned substrate with several MoSe₂ monolayer crystals transferred on to it. The MoSe₂ film between the source (S) and drain (D) electrodes of the device lies within the dotted oval. A magnified view of this oval is shown in the upper right corner. Figure 2(b) is the same as panel 2(a) but shows the IL placed over the active portion of the MoSe₂ film. This gel consists of 1-ethyl-3-methylimidazolium bis(trifluromethylsulfonyl) amide and poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer dissolved in methylene chloride as reported elsewhere.¹³ A 25μm diameter gold wire inserted into the gel served as the gate (G) electrode, while the S and D terminals were hard wired with Ag epoxy and Au wire. All measurements were performed in vacuum (10^-2 Torr) (to minimize the effects of moisture absorbed by the IL), under ambient light and at room temperature (295K) with S grounded (i.e. 0V). Figure 2(c) shows the schematic diagram of the external electrical connections used for device characterization. V_DS and V_GS represent the drain-source and gate-source voltages that were supplied by a Keithley model 6517A electrometer and model 2400 source meter respectively and that also measured the corresponding currents. The active MoSe₂ channel has length L = 20μm and width W = 280μm. Prior to electrical characterization, the IL specific capacitance (C_i) was measured by placing a drop between two plates in a parallel plate capacitor. This capacitor was formed by modifying a Hewlett Packard 16453A dielectric test fixture. Figure 2(d) shows C_i measured using an Agilent Technologies 4294A impedance analyzer at a fixed exciting voltage of 500 mV in the frequency range 40Hz – 1MHz in air, and the inset shows a schematic of the capacitor where the plate separation was 100μm. The high specific capacitance approaching 7 μC/cm² at low frequencies results from the formation of an electric double layer at the metal/IL interfaces with sub-nm thickness, and is responsible for the electrostatic field effect seen in our device at low operating voltages. In comparison, the specific capacitance of a 20nm - 150nm thick SiO₂ layer is in the range: 20nF/cm² < C_i < 1.1μF/cm². Figure 2(e) shows the energy level schematic of Au and monolayer MoSe₂ with reference to vacuum (E_vac) prior to physical contact between the two. We assume 5.1 eV as the work function energy for Au,¹⁴ the electron affinity of monolayer MoSe₂ is 3.91 eV¹⁵ and its band gap is 1.55eV¹ with the Fermi energy lying close to the mid-gap position.¹⁶ Band bending at the interface upon physical contact (Au/MoSe₂) in thermal equilibrium is anticipated to result in Schottky barriers to electron or hole transport.

In order to evaluate the electrical performance and usefulness in practical circuits, monolayer MoSe₂ was characterized in a FET configuration using an IL as the gate dielectric. Figure 3(a) shows the variation of I_DS plotted on a log scale as the gate voltage (V_GS) is swept at 40 mV/s with the drain (V_DS) held constant at +0.5V. An increase in I_DS for positive and negative V_GS indicates ambipolar charge transport in the MoSe₂ channel.⁴ When V_GS is greater than the threshold voltage for electron accumulation (-0.2V), electrons (e) are injected from the source into the conduction band of MoSe₂ and drift toward the drain. This is shown schematically in the band diagram for n-FET operation in the red inset to Figure 3(a). When V_GS is less than the threshold voltage for hole accumulation (-1.8V), holes (h) are injected from the drain into the valence band of MoSe₂ and drift toward the source. This is shown schematically in the band diagram for p-FET operation in the green inset to Figure 3(a). The threshold voltages mentioned above were obtained from the intercepts of straight lines drawn through the steepest parts of the n- and p-branches of the data shown in Figure 3(a) with the voltage axis. The band diagrams presented in Figure 3 are not drawn to scale. They schematically illustrate the barriers to charge transport via band bending that occurs at the metal/semiconductor interface only, and not the larger portion of the semiconducting channel between the S and D contacts. The upper inset to Figure 3(a) shows the output characteristics (I_DS vs. V_DS) for V_GS=0V. The nearly symmetric but non-Ohmic curve at zero gate voltage is due to back-to-back Schottky barriers formed via band bending at the two Au/MoSe₂ contacts of the device. Although the contact resistance in our device is finite and can be extracted in principle using a modified Y-function method,¹⁷ we assume that it does not degrade device performance since the application of a gate voltage to the IL results in linear I_DS-V_DS curves at low V_DS (<0.1V). Also, as reported in a MoS₂ FET gate with an IL as the gate dielectric,¹⁸ we suggest that the application of a gate voltage to the IL thins the Schottky barriers in our device via accumulation of large amounts of charge carriers that effectively screen out extrinsic scattering by charged impurities further reducing the contact resistance. The inset to Figure 3(a) also shows that the currents in the off state at low voltage (-0.1 < V_DS < 0.1V) are in the few pA range, making the on/off ratio of our device ∼10⁶ for both holes and electrons. Applying a fixed -0.5V to the drain resulted in a similar shape of the I_DS vs. V_GS curve as seen in Figure 3(a) (data not shown) but with data lying in the third and fourth quadrant since the measured currents are negative. Under these conditions, during n-FET operation, electrons are injected into the conduction band of MoSe₂ from the drain, while in p-FET mode, holes are injected into the valence band from the source.

The difference in the gate voltage taken from the onset of n-FET to the onset of p-FET operation is proportional to the band-gap of MoSe₂. From Figure 3(a) we see that E_G ∼1.6eV, slightly larger than the reported value. This could be due to the finite potential difference between the gate electrode and the ionic liquid.¹⁹ The larger negative gate voltage needed to initiate p-type operation and reach the same I_DS is indicative that MoSe₂ is electron doped at V_GS=0V. The leakage gate current through the ionic liquid reached 0.5nA and -8nA under n- and p-FET operation modes and was several orders of magnitude smaller than the channel current under all measurement conditions. Figure 3(b) shows I_DS vs. V_GS for various (fixed) V_DS voltages on a different device. The gate voltage was swept at 10mV/s. The slower sweep rate resulted in a slightly larger hysteresis due to the slow motion of the ions in the IL to changes in the gate voltage.²⁰ Clear ambipolar charge transport is seen in all plots with the hole and electron currents increasing as V_DS is increased. A larger increase however in the hole current (compared to the electron current) implies that the channel is electrostatically doped to a higher level as V_DS is made more positive, this in turn makes the Schottky barrier width at the drain/MoSe₂ contact thinner allowing for easier tunneling of holes into the valence band of MoSe₂ in addition to thermionic emission over the barrier.²¹ Also, as seen in the band diagram green inset to Figure 3(a), the barrier height is higher for electron injection into the conduction band of MoSe₂ from the source terminal than for hole injection into the valence band of MoSe₂ from the drain terminal. Further characterization of the device focused on the p-FET and n-FET operation separately.

Figure 4(a) shows the drain-source current (I_DS) as a function of the drain-source voltage (V_DS) for various V_GS voltages applied to the IL. Figure 4(b) shows the device transconductance I_DS vs. V_GS curve with V_DS fixed at +0.5V, while the gate voltage is swept at 40mV/s. An increase in the channel current for increasing positive V_GS indicates that the induced electrostatic charges are electrons and the device operates in the n-FET mode. Current saturation was not observed in the window of the V_DS sweep up to +0.5V in Figure 4(a), but a tendency to saturate is seen for higher V_DS. The super-linear variation in I_DS for V_DS < 0.1V implies that the Schottky barriers at the contacts are lowered via band bending, and the contact resistance does not significantly affect device operation. This results in efficient electron injection into the conduction band from the source electrode (likely via tunneling) as indicated in the inset to Figure 4(b). From the linear portion of the I_DS-V_GS curve plotted on a linear scale, the device trans-conductance (⁠$gm=dIDSdVGS$⁠) was 32 μA/V from which the electron mobility (⁠$μ=gmLWCiVDS$⁠) was calculated as 0.6 cm²/V-s and the on/off ratio was ∼3x10⁶. The sub-threshold swing measured along the steepest straight line section of Figure 4(b) was 100 mV/decade with the onset of n-FET operation at ∼ -0.2V. The transfer process typically leads to the presence of folds or wrinkles on the MoSe₂ surface.⁴ Combined with the roughness at the substrate/MoSe₂ interface, the measured mobility is reasonable for our device with bottom contacts. Higher mobility values up to 50 cm²/V-s at room temperature have been reported for MoSe₂ by others on exfoliated flakes^2,22 and for CVD grown MoSe₂ monolayers on the as prepared substrate.^5,23 Fabricating devices on the as prepared substrates (no transfer required) is anticipated to yield higher mobility for holes and electrons.

Analyzing the p-type FET operation shown in Figures 4(c) and (d) yield a hole mobility of 0.1 cm²/V-s with an on/off ratio of ∼1x10⁶, a sub-threshold swing of 100 mV/decade with the onset of p-FET operation at ∼ -1.8V. A slightly higher mobility for electrons suggest that n-type behavior is more favorable for MoSe₂. These parameters are comparable or better than that reported for a MBE grown monolayer MoSe₂.⁴ The mobility values extracted from the output curves of Figures 4(a) and 4(c) via the standard FET equation $IDS=μWCi(VGS−VTH)22L$ where V_TH is the threshold voltage, yield values similar to those calculated from the trans-conductance curves of Figures 4(b) and 4(d). The electrostatic charge induced carrier density (⁠$n∼Ci(VGS−VTH)e$⁠) was calculated to be 6x10¹³/cm² and 4x10¹³/cm² for electrons and holes respectively, higher than that reported using a 90 nm thick SiO₂ gate dielectric.²² Using an IL as the gate dielectric has the advantage of having a large specific capacitance and of being able to accumulate carrier’s two orders of magnitude higher than conventional dielectrics²⁰ with concomitant reduction in the operating voltages. The similarity in the values of the device parameters extracted for hole and electron transport shows that the Schottky barrier height and width are easily tunable in MoSe₂ permitting easy flow of electrons and holes from the channel into the same contact metal and vice versa. These results are also consistent with a low level of Se vacancies in MoSe₂ that result in the Fermi level being located closer toward the center of the band as in an intrinsic semiconductor. The high on/off ratio, mobility and induced charge density, together with enhanced gate control of the channel currents via the steep sub-threshold makes this device suitable for gate controlled on/off switches.

An inverter with a resistive load was designed to test the binary operation of the monolayer MoSe₂ based FET. Figure 5 shows the output (V_OUT) vs. input voltage (V_IN) under n-FET operation (V_DS = +1V fixed) and the inset shows the schematic of the electrical connections. The high on/off ratio and reasonable mobility in MoSe₂ were essential for successful operation as a binary switch. For low V_IN the device is off, resulting in no voltage drop across the load and V_OUT is set high. At high V_IN the device is on, resulting in a large voltage drop across the load and pulling V_OUT down to the low state. The result is that the output voltage is switched between the on (>0.9V) and the off (<0.1V) states within 0.5V of the input voltage swing. The circuit gain (⁠$dVOUTdVIN$⁠) also plotted in Figure 5 shows that it has a value ∼2, and the device is therefore capable of driving transistor logic circuits cascaded in series. The near symmetric shape of the gain plot about the maximum ensures a similar turn on/turn off characteristic for the device. In addition, depending on the supply voltage polarity, these ambipolar inverters work for both + or – V_IN and V_OUT thus expanding their use in switching circuits operating under either hole or electron transport modes. The possibility of radiative recombination of electrons and holes during ambipolar operation could further extend the use of this device to optoelectronic applications.

In conclusion, CVD grown MoSe₂ monolayer FET gated via an IL exhibits ambipolar charge transport at low operating voltages and at room temperature. IL gating reduces Schottky barriers at the metal/semiconductor interface, assisting band bending and permitting efficient flow of electrons and holes into the MoSe₂ channel. The mobility, on/off ratio, sub-threshold swing and induced charge density for hole and electron transport are higher than reported values for substrate transferred MoSe₂ monolayers synthesized and characterized under like conditions. These device parameters are also similar for both hole and electron transport enabling its use interchangeably as an n- or a p-FET. Fabricating the device on the growth substrate may improve the mobility by avoiding defects introduced via the transfer process. The use of a common metal for contacts simplifies the fabrication process and testing the device as an inverter yielded a gain ∼2, making it capable of driving additional binary based logic devices.

This work was supported in part by NSF grants DMR PREM 1523463, DMR RUI 1360772 and EFRI 2-DARE 1542879.