Despite the challenges associated with the cost and technological innovation, the semiconductor industry has introduced nanoelectronics into the market place. By extending traditional CMOS (complimentary metal oxide semiconductor transistors) through new materials in both the devices and on‐chip interconnect, planar CMOS is already manufactured with transistor gate lengths less than 50 nm. Further extending CMOS will not only require new materials, but it may also drive the use of new non‐planar device structures for transistors and new approaches for on and off‐chip interconnection. At some point, CMOS extension may no longer be possible, and then a new switch would be necessary. The transition between CMOS extension and planar CMOS could involve the gradual incorporation of Beyond CMOS technology. The number of candidates continues to grow even as some possible technology is removed from consideration. Characterization and Metrology is finding each step in this transition to be a great challenge. This paper overviews the characterization and metrology necessary for both CMOS extension and beyond CMOS semiconductor technology. The International Technology Roadmap for Semiconductors is used a guide that provides a roadmap for both metrology and process technology that extends to beyond CMOS materials and devices.(1)
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26 September 2007
CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology
27–29 March 2007
Gaithersburg (MD)
Research Article|
September 26 2007
Characterization and Metrology for Nanoelectronics
Alain C. Diebold
Alain C. Diebold
College of Nanoscale Science and Engineering University at Albany Albany, NY 12203
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AIP Conf. Proc. 931, 20–33 (2007)
Citation
Alain C. Diebold; Characterization and Metrology for Nanoelectronics. AIP Conf. Proc. 26 September 2007; 931 (1): 20–33. https://doi.org/10.1063/1.2799372
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