This paper reports on the design and chip measurements from a CMOS chaotic oscillator operating by itself and connected in a ring of four similar oscillators. The oscillator is autonomous and generates signals with three state variables analogous to Chua’s circuit. For commensurate bandwidth, this design utilizes currents and capacitors over 200 times smaller than above threshold CMOS realizations. Also, all circuit elements are on chip. The resulting voltage-controlled bifurcation parameters simplify exploration of the circuit’s dynamics, alleviating the need to interchange physical components. This combination of reduced size and variable parameters make the design suitable for single-chip VLSI synthesis of higher dimensional chaotic circuits, including coupled maps generating spatio-temporal chaos and systems exploiting chaos synchronization.
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Research Article| May 15 1997
Spatio-temporal simulation in subthreshold CMOS
AIP Conf. Proc. 411, 255–260 (1997)
John Neeley, John G. Harris; Spatio-temporal simulation in subthreshold CMOS. AIP Conf. Proc. 15 May 1997; 411 (1): 255–260. https://doi.org/10.1063/1.54227
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