Implementation of delayed LMS algorithm based adaptive filter using Verilog HDL

Implementation of a Delayed LMS algorithm(D-LMS) based adaptive filter using in Verilog HDL. The structure of the LMS algorithm-based adaptive filter has a longer critical path, an efficient structure for the execution of the LMS algorithm having a lower critical path, called D-LMS is discussed. The D-LMS will be implemented in Verilog HDL. For the design of the D-LMS adaptive filter, necessary building blocks, such as block carry look-ahead adder (BCLA) & multiplier are discussed. These circuits are efficiently used to implement D-LMS adaptive filter. The whole system is designed using Verilog HDL and synthesized using Xilinx ISE software. The detailed synthesis report along with the RTL schematic will be presented.