In this paper, the simulation of various XOR-XNOR gates are implemented and novel 1-bit Full Adder (FA) using mirror circuits and the transistor sizing method, which uses a numerical computational PSO algorithm to reduce the size of the transistors, are simulated. These two techniques allow for greater optimization in terms of power consumption and delay. These circuits will be simulated using the Cadence Virtuoso tool and a 180nm technology model. In this comparison, the effects of various factors, such as supply voltages, threshold voltages, and output capacitances, result in a reduction of the Power Delay Product (PDP) and Energy Delay Product (EDP) by up to 23.4 % and 43.5 %, respectively.

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