Division is a time-consuming and computationally difficult operation that takes more time and space to implement than the other arithmetic operations. In today’s binary world of high-speed computing, it’s critical to have ways for executing arithmetic operations that are both time and space economical. Any processor’s performance is solely determined by its power, area, and delay. A processor’s power, area, and delay should all be low in order for it to be effective. Division algorithms, which are based on ancient Indian Vedic mathematic concepts, minimize the processor’s space and time. Vedic Mathematics is a superior way of computation since it is founded on the laws that govern the human intellect. "Nikhilam Sutra", an ancient Vedic mathematic technique can be used to achieve a good performance by reducing propagation delay and area usage. Xilinx ISE 14.7 can be used to accomplish this division algorithm’s operation. The proposed design is compared with current divider architectures that are implemented on an FPGA, such as the Non-restoring Algorithm based Divider and other Vedic Dividers (Paravartya Sutra, Nikhilam Sutra).

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