The goal of VLSI design is to increase speed while lowering space, power, and delay requirements. One of the key topics of research in VLSI system design is the development of a digital adder with the best possible area and speed. An arithmetic logic unit serves as the fundamental component of microprocessors, microcontrollers, and digital signal processors (ALU). The adder design of an ALU determines its performance. The Carry Propagation Delay (CPD), area, and power are crucial parameters for the adder’s structure. The carry choose strategy has been identified as a good cost, performance trade-off in the design of carry propagation adders. However, the conventional carry select adder (CSLA) still takes up a lot of room because of the twin ripple carry adder structure. Numerous authors put up various ideas to lessen the carry select adder’s area, power and delay. In this article, we’ll contrast the solutions and conclusions of those authors.

1.
Srikanth
,
Y.
, et al "Area-Power Analysis of Carry Select Adder using Transmission gates."
IOP Conference Series: Materials Science and Engineering
. Vol.
981
. No.
3
.
IOP Publishing
,
2020
.
2.
Ahmed
,
L. Jubair
et al "Biomedical Image Processing with Improved SPIHT Algorithm and optimized Curvelet Transform Technique."
2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS
). Vol.
1
.
IEEE
,
2021
.
3.
Sireesha
,
P.
, et al "Design and analysis of 32-bit high-speed carry select adder."
Journal of Physics: Conference Series
. Vol.
1916
. No.
1
.
IOP Publishing
,
2021
.
Hebbar
,
Piyush
Srivastava
,
Vinod Kumar
Joshi
2018
Design of High-Speed Carry Select Adder using Modified Parallel Prefix Adder
.
4.
Gokulavasan
,
B.
, et al "Smart Gas Booking System and Leakage Detection Using IOT."
2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS
). Vol.
1
.
IEEE
,
2022
.
5.
KK
,
Mohamed Salih
. "
Efficient carry select adder design for FPGA implementation
."
Procedia Engineering
30
(
2012
):
449
456
.
6.
You
,
Heng
, et al "
An energy and area efficient carry select adder with dual carry adder cell
."
Electronics
8
.
10
(
2019
):
1129
.
7.
Kadam
,
D. B.
,
K. K.
Pandyaji
, and
Kazi Kutubuddin Sayyad
Liyakat
. "
Implementation of Carry Select Adder (CSLA)for Area, Delay and Power Minimization
."
Telematique
(
2022
):
5461
5474
.
8.
Mr.
M.
Prasannakumar
,
Dr.
R.
Thangavel
2021
Implementation of Carry Select Adder based Vedic Multiplier for minimizing the path delay and to increase the efficiency of the processor.
9.
Abhishek R.
Hebbar
,
Piyush
Srivastava
,
Vinod Kumar
Joshi
2018
Design of High-Speed Carry Select Adder using Modified Parallel Prefix Adder
.
10.
Chittaluri
Bhaskar
,
Kota Nageswara
Rao
2019
Using the Verilog language, Design a low power and area-efficient Carry Select Adder
.
This content is only available via PDF.
You do not currently have access to this content.