A five-phase multilevel inverter (MI) that has a lower number of power semiconductor switches is proposed. Compared to cascaded H-bridge multilevel inverter (CHBMI), the proposed MI has a lower number of power semiconductor switches. For example, a five-phase seven-level CHBMI consists of 60 power semiconductor switches while the proposed MI has 40 power semiconductor switches, which is reduced by 20 switches or 33.33 %. The switching angles implemented to the proposed MI are obtained using selective harmonic minimization pulse-width modulation (SHMPWM) technique solved by particle swarm optimization (PSO) algorithm. Simulation is carried out using PSIM software to verify the performance of the proposed MI and the simulation results show that the proposed MI can synthesize a sinusoidal-like staircase output voltage waveform.

Topics
Inverters, Semiconductor switch, Pulse width modulation, Mathematical optimization
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