Optimization and analysis of FPGA-based systolic array for matrix multiplication

Over the years, field-programmable gate array (FPGA)-based accelerators have attracted interest and attention due to their performance and energy efficiency factors. This paper presents an optimized FPGA-based accelerator using a systolic array for matrix multiplication. In a systolic array, many identical processing elements (PEs) are arranged in a well-organized structure, and each PE is connected with the other PEs. The data will flow between neighboring elements in different directions synchronously. PE is an arithmetic logic unit (ALU) with attached working registers and local memory. This paper coded the accelerator in Verilog and simulated using the Quartus Prime with PowerPlay Power Analyzer tool for power optimization. A 3-bit ALU has been implemented using the Synopsys electronic design automation (EDA) tool. The schematic diagram, layout and verification for a complete ALU design have been accomplished. This paper provides detailed results and analyses of the systolic array and ALU in power dissipation and area density based on method and circuit implementation. The results showed that the power consumption efficiency of the accelerator improved after optimization. Also, power dissipation and the area of 3-bit ALU are reduced by 0.2 mW and 4.55 % at the back-end, respectively.