In modern systems, the square root of a number is calculated using the long division method. The radical can be calculated using several diverse approaches. This study focuses on one such method that, when applied to specific numbers, such as perfect square numbers, yields fewer complex results. The model utilized in this study is based on old Vedic mathematics sutras and can be used for chip designs as well. There is always a desire to have a highly optimized technique for quickly calculating mathematical operations. The proposed method focuses on minimizing the number of Logic elements and the complexity of the computation in terms of speed and power dissipation. The designs are coded in Verilog HDL and synthesized with Altera Quartus II 13.1. device chosen was cyclone IV. The power dissipation for proposed shows 3mW improvement and logic element shows 2 % improvement. Results clearly indicate the better power performance of our proposed Vedic multiplier.
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