In this paper, some changes carried out in the LDMOS known as MOSFET1 by utilizing trench known as MOSFET2. In the proposed device silicon material acts as channel material and the gate electrode is placed in oxide trenches. The drain contact is positioned at the centre and the sources are located at the edges. In the MOSFET2, two gates creating the two channels. Channels acts together so produce large gain, current, and voltage need for the power IC. An extension in breakdown occurs due to the RESURF in MOSFET2. With the help of simulator the performance are analysed with that of the MOSFET1. The MOSFET2 gives 111% improvement in gain, 12% decrease the threshold-voltage, 2 times higher output current in comparison with the MOSFET1. The performance of the MOSFETs is investigated by device simulator ATLAS. The proposed device is suitable for analog applications.
Skip Nav Destination
Article navigation
8 September 2023
PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON MATERIALS FOR EMERGING TECHNOLOGIES: ICMET-2021
18–19 February 2022
Phagwara, India
Research Article|
September 08 2023
Study of silicon material MOS with low threshold potential Available to Purchase
Manoj Singh Adhikari;
Manoj Singh Adhikari
a)
School of Electronics and Electrical Engineering, Lovely Professional University
, Phagwara, Punjab, India
Search for other works by this author on:
Yogesh Kumar Verma;
Yogesh Kumar Verma
b)
School of Electronics and Electrical Engineering, Lovely Professional University
, Phagwara, Punjab, India
Search for other works by this author on:
Subhash Suman
Subhash Suman
c)
School of Electronics and Electrical Engineering, Lovely Professional University
, Phagwara, Punjab, India
c)Corresponding author: [email protected]
Search for other works by this author on:
Manoj Singh Adhikari
a)
School of Electronics and Electrical Engineering, Lovely Professional University
, Phagwara, Punjab, India
Yogesh Kumar Verma
b)
School of Electronics and Electrical Engineering, Lovely Professional University
, Phagwara, Punjab, India
Subhash Suman
c)
School of Electronics and Electrical Engineering, Lovely Professional University
, Phagwara, Punjab, India
AIP Conf. Proc. 2800, 020146 (2023)
Citation
Manoj Singh Adhikari, Yogesh Kumar Verma, Subhash Suman; Study of silicon material MOS with low threshold potential. AIP Conf. Proc. 8 September 2023; 2800 (1): 020146. https://doi.org/10.1063/5.0164913
Download citation file:
Pay-Per-View Access
$40.00
Sign In
You could not be signed in. Please check your credentials and make sure you have an active account and try again.
20
Views
Citing articles via
Effect of coupling agent type on the self-cleaning and anti-reflective behaviour of advance nanocoating for PV panels application
Taha Tareq Mohammed, Hadia Kadhim Judran, et al.
Design of a 100 MW solar power plant on wetland in Bangladesh
Apu Kowsar, Sumon Chandra Debnath, et al.
With synthetic data towards part recognition generalized beyond the training instances
Paul Koch, Marian Schlüter, et al.
Related Content
Demonstration and analysis of a 600 V, 10 A, 4H-SiC lateral single RESURF MOSFET for power ICs applications
Appl. Phys. Lett. (May 2019)
Fully tensile strained partial silicon-on-insulator n-type lateral-double-diffused metal-oxide-semiconductor field effect transistor using localized contact etching stop layers
AIP Advances (May 2017)
Design methodologies and fabrication of 4H-SiC lateral Schottky barrier diode on thin RESURF layer
Appl. Phys. Lett. (March 2022)
Deep depletion concept for diamond MOSFET
Appl. Phys. Lett. (October 2017)
Ultra-low reverse leakage in large area kilo-volt class β-Ga2O3 trench Schottky barrier diode with high-k dielectric RESURF
Appl. Phys. Lett. (December 2023)