The main objective behind this proposed design is to reduce the low offset voltage for the minimum value, so that its effect is reduced by two stage CMOS operational amplifier. The majority of operational amplifiers mainly consist of two inputs and one output. The signal coming out from the amplifiers is a description of the distinction and comparison between any two input signals that are independent on each other. Practically no voltage appears on the output and the offset voltage is close to zero in the event that there is no difference between the two input signals. In this paper, comprising two proposed circuits are designed and simulated using OrCAD PSpice 17.4, first, a circuit consisting of two stages is designed for a 180 nm technology operational amplifier, a designed two-stage amplifier circuit consisting of eight semiconductor switches (MOSFET). Second, a proposed circuit consist of a two stage OPAMP in conjunction with an auxiliary OPAMP. In the two proposed circuits, the MOSFET parameters are designed and excellent results obtained, including reduction of offset voltage and preservation of the gain value, where the offset voltage value of the Two-stage circuit was 71 µv and the offset value of the proposed design was equal to 21 µv as the offset voltage was improved and reduced by 70 %.

1.
S.
Bandyopadhyay
, et al, “
Design of Two Stage CMOS Operational Amplifier in 180nm Technology with Low Power and High CMRR
”,
International Journal on Recent Trends in Engineering & Technology
, Vol.
11
, PP
239
247
,
2014
2.
R. B.
Reddy
and
Sh. K.
Gowda
, “
Design and Analysis of CMOS Two Stage OP-AMP in 180nm and 45nm Technology
”,
International Journal of Engineering Research & Technology (IJERT)
, Vol.
4
, PP
1100
1103
,
2015
3.
R.
Chaudhari
and
R.
Soni
, “
Design and Characterization of two stage High-Speed CMOS Operational Amplifier
”,
Rahul Chaudhari et al Int. Journal of Engineering Research and Applications
, Vol.
4
, PP.
536
541
,
2014
.
4.
M. J.M.
Pelgrom
, et al, “
Transistor Matching in Analog CMOS Applications
, ”,
in Applied. of Technical Digest of International Electron Devices Meeting, Cat. No. 98CH36217
, pp.
915
918
,
1998
.
5.
S. Alam
Chowdhury
, et al, “
Design of a Two Stage CMOS Operational Amplifier in 100nm Technology with Low Offset Voltage
”,
In: Applied. Of International Conf. On Innovations in Science, Engineering and Technology (ICISET), Chittagong, Bangladesh
, PP.
56
59
,
2018
6.
J-Y.
Zhang
, et al, “
Design of low-offset low-power CMOS amplifier for biosensor application
”,
Journal of Biomedical Science and Engineering
, Vol.
2
, No.
7
, pp.
538
542
,
2009
.
7.
D.
DZAHINI
and
H.
Ghazlane
, ”
A very low offset voltage auto−zero stabilized CMOS operational amplifier
”,
Workshop on Electronics for LHC Experiments 8
, pp.
1
3
, (
2002
).
8.
M.
Miyahara
and
A.
Matsuzawa
, “
A Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique
”,
in Applied of sian Solid-State Circuits Conference
, pp.
233
236
, (
2009
).
9.
H.
Jeon
and
Y.gBin
Kim
, “
A CMOS LOW-POWER LOW-OFFSET AND HIGH-SPEED FULLY DYNAMIC LATCHED COMPARATOR
”,
in Applied of International SOC Conference
, pp.
285
288
, (
2010
).
10.
H.
Jeon
, et al, “
offset Voltage Analysis of Dynamic Latched Comparator
”,
In International Midwest Symposium on Circuits and Systems (MWSCAS)
, pp.
1
4
, (
2011
).
11.
Ch.
Chan
, et al, “
A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS
”,
in Applied of Asian Solid-State Circuits Conference
, pp.
233
236
, (
2011
).
12.
H. Jun
Jeon
and
Y.
Kim
, “
A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator
”,
Integrated Circuits and Signal Processing
, Vol.
70
, No.
3
, pp.
337
346
, (
2012
).
13.
S.
Babayan-Mashhadi
and
R.
Lotfi
, “
An offset cancellation technique for comparators using body-voltage trimming
Analog Integrated Circuits and Signal Processing
, Vol.
73
, No.
3
, pp.
673
682
, (
2012
).
14.
M. Hassan
pourghadi
, et al, “
A low-power low-offset dynamic comparator for analog to digital converters
”,
Microelectronics Journal
, Vol.
45
, No.
2
, pp.
256
262
, (
2014
).
15.
M. Mohammadi
Khanghah
and
K. Dabbagh
Sadeghipour
, “
A 0.5 V offset cancelled latch comparator in standard 0.18 lm CMOS process
”,
Analog Integrated Circuits and Signal Processing
, Vol.
79
, No.
1
, pp.
161
169
, (
2014
).
16.
V.
Raghuveer
, et al, “
A 2 µV Low Offset, 130 dB High Gain Continuous Auto Zero Operational Amplifier
”,
inApplied ofS International Conference on Communication and Signal Processing
, pp.
1715
1718
, (
2017
).
17.
L.
Kouhalvandi
, et al, “
10-bit High Speed CMOS Comparator with Offset Cancellation Technique
”,
Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE),
pp.
1
4
, (
2017
).
18.
A. K.
Dubey
and
R.K.
Nagaria
, “
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load
”,
Microelectronics Journal
, Vo.
78
, pp.
1
10
, (
2018
).
19.
P.P.
Gandhi
and
N. M.
Devashrayee
, “
A novel low offset low power CMOS dynamic comparator
”,
Analog Integrated Circuits and Signal Processing
, Vol.
96
, No.
1
, pp.
147
158
, (
2018
).
20.
D.
Erol
,
A.
Dŏguş G¨ung¨ord¨u
,
G.
D¨undar
and
M. Berke
Yelten
An Offset Cancellation Set-up for Amplifiers Subject to Aging
”,
In: Proc. Of International Conference on Electrical and Electronics Engineering (ELECO
), pp.
384
387
.(
2019
).
21.
R. Chen-Hao
Chang
, et al, “
A 93.4% Efficiency 8mV Offset Voltage Constant On -Time Buck Converter with An Offset Cancellation Technique
”,
Transactions on Circuits and Systems II
, Vol.
67
, No.
10
, pp.
2069
2073
, (
2019
).
22.
K.
Bandla
,
H.
krishnan
, and
D.
PalSMIEEE
, “
Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC
”,
in Applied of International Conference on Innovative Trends in Communication and Computer Engineering (ITCE), Aswan, Egypt
, pp.
299
302
, (
2020
).
23.
E.
Alnasser
, “
A Novel Low Output Offset Voltage Charge Amplifier for Piezoelectric Sensors
”,
IEEE SENSORS JOURNAL
, Vol.
20
, No.
10
pp
5360
5367
, (
2020
).
24.
E.
Choa
, et al, “
Radiation Hardened Op-amp Design for 1 Mrad TID
”,
Transactions of the Korean Nuclear Society Virtual Spring Meeting
,
2020
.
25.
A.
Sheeparamatti
, et al, “
Design of 3.3V Rail To Rai Operational Amplifier for High Resolution ADC] Driver Amplifier
”,
in Applief of International Conference Innovative Mechanisms for Industry Applications
, pp
317
320
,
2017
.
26.
Kavyashree
C L
, et al S. MP, “
Design and Implementation of two stage CMOS Operational amplifier using 90nm technology
”,
in Applied of International Conference on Inventive Systems and Control
, pp.
1
4
,(
2017
).
27.
G.
Venkatrao
, et al, ”
Design of Low Power and High CMRR Two Stage CMOS Operational Amplifier in 180nm Technology
International Journal of Innovative Research in Science, Engineering and Technology
, Vol.
5
, Issue
5
,pp.
6746
6752
, May (
2016
).
28.
D.
Nageshwarrao
, et al, “
IMPLEMENTATION AND SIMULATION OF CMOS TWO STAGE OPERATIONAL AMPLIFIER
”,
International Journal of Advances in Engineering & Technology
, Vol.
5
, No.
2
, pp.
162
167
, (
2013
).
29.
Shubham
Sharma
&
Ahmed J.
Obaid
(
2020
)
Mathematical modelling, analysis and design of fuzzy logic controller for the control of ventilation systems using MATLAB fuzzy logic toolbox
,
Journal of Interdisciplinary Mathematics
,
23
:
4
,
843
849
, DOI: .
This content is only available via PDF.
You do not currently have access to this content.