The binary addition is an exceptionally essential activity performed in any computerized circuit and in this way, adders are the most basic units in any advanced outline, even extensive and complex plans utilize parallel adders for its task. Such huge numbers of other circuit are additionally made by utilizing Full adders like Multiplexers and amid the most recent decade, the span of gadgets are diminishing definitely and requires low power utilization for its activity and for the lessening of energy in the entire gadget we first need to diminish the power utilization of sub frameworks utilized as a part of the gadget.
REFERENCES
1.
Fu-Chiung
Cheng
, S. H.
Unger
, and M.
Theobald
, “Self-timed carry-lookahead adders
,” IEEE Trans. Comput.
, vol. 49
, no. 7
, Jul. 2000, doi: .2.
F. C.
Cheng
, S. H.
Unger
, and M.
Theobald
, “Self-timed carry-lookahead adders
,” IEEE Trans. Comput.
, vol. 49
, no. 7
, pp. 659
–672
, 2000
, doi: .3.
M.
Anis
, M.
Allam
, and M.
Elmasry
, “Impact of technology scaling on CMOS logic styles
,” IEEE Trans. Circuits Syst. II Analog Digit. Signal Process.
, vol. 49
, no. 8
, pp. 577
–588
, 2002
, doi: .4.
A.
De Graaf
, Principles of Asynchronous Circuit Design. Boston, MA
: Springer US
, 2001
.5.
R.
Ye
, T.
Wang
, F.
Yuan
, R.
Kumar
, and Q.
Xu
, “On reconfiguration-oriented approximate adder design and its application,
” IEEE/ACM Int. Conf. Comput. Des. Dig. Tech. Pap. ICCAD
, pp. 48
–54
, 2013
, doi: .6.
D.
May
and W.
Stechele
, “Design of fine-grained sequential approximate circuits using probability-aware fault emulation
,” Proc. Int. Symp. Low Power Electron. Des.
, vol. 2015-September, pp. 73
–78
, 2015
, doi: .7.
R.
Venkatesan
, A.
Agarwal
, K.
Roy
, and A.
Raghunathan
, “MACACO: Modeling and analysis of circuits for approximate computing,
” IEEE/ACM Int. Conf. Comput. Des. Dig. Tech. Pap. ICCAD
, pp. 667
–673
, 2011
, doi: .8.
D.
Mohapatra
, V. K.
Chippa
, A.
Raghunathan
, and K.
Roy
, “Design of voltage-scalable meta-functions for approximate computing
,” Proc. -Design, Autom. Test Eur. DATE
, pp. 950
–955
, 2011
, doi: .9.
N.
Tiwari
, R.
Sharma
, and R.
Parihar
, “Implementation of area and energy efficient full adder cell,
” Int. Conf. Recent Adv. Innov. Eng. ICRAIE 2014
, 2014
, doi: .10.
I.
Hassoune
, D.
Flandre
, I. O‟
Connor
, and J. D.
Legat
, “ULPFA: A new efficient design of a power-aware full adder
,” IEEE Trans. Circuits Syst. I Regul. Pap.
, vol. 57
, no. 8
, pp. 2066
–2074
, 2010
, doi: .11.
D.
Chaudhuri
, A.
Nag
, and S.
Bose
, “Low Power Full Adder Circuit Implemented In Different Logic
,” Int. J. Innov. Res. Sci. Eng. Technol.
, vol. 3
, no. 6
, pp. 124
–129
, 2014
.12.
A.
Morgenshtein
, A.
Fish
, and I. A.
Wagner
, “Gate-diffusion input (GDI): A power-efficient method for digital combinatorial circuits
,” IEEE Trans. Very Large Scale Integr. Syst.
, vol. 10
, no. 5
, pp. 566
–581
, 2002
, doi: .13.
M.
Shoba
and R.
Nakkeeran
, “GDI based full adders for energy efficient arithmetic applications
,” Eng. Sci. Technol. an Int. J.
, vol. 19
, no. 1
, pp. 485
–496
, 2016
, doi: .14.
15.
P.
Verma
, R.
Singh
, and Y. K.
Mishra
, “Modified GDI Technique - A Power Efficient Method For Digital Circuit Design,”
vol. 2055
, no. 5
, pp. 1071
–1080
, 1956
.16.
M.
Gao
, Q.
Wang
, T.
Arafin
, and C.
Park
, “for Low Power and Security in the Internet of Things
,” pp. 27
–34
, 2020
.17.
J. S.
Chohan
, R.
Singh
, and K. S.
Boparai
, “Post-processing of ABS Replicas with Vapour Smoothing for Investment Casting Applications
,” Proc. Natl. Acad. Sci. India Sect. A Phys. Sci., Feb.
2020
, doi: .18.
H.
Cao
, S.
Wu
, G. S.
Aujla
, Q.
Wang
, L.
Yang
, and H.
Zhu
, “Dynamic Embedding and Quality of Service-Driven Adjustment for Cloud Networks
,” IEEE Trans. Ind. Informatics
, vol. 16
, no. 2
, pp. 1406
–1416
, 2020
, doi: .19.
A.
Choudhary
, M. K.
Gupta
, and M.
Kumar
, “Investigating the effect of electrode preheating in novel water-cooled advanced submerged arc welding process
,” Proc. Inst. Mech. Eng. Part L J. Mater. Des. Appl.
, vol. 233
, no. 10
, pp. 2015
–2029
, Oct. 2019
, doi: .20.
R.
Singh
, J. S.
Dureja
, M.
Dogra
, M. K.
Gupta
, M.
Mia
, and Q.
Song
, “Wear behavior of textured tools under graphene-assisted minimum quantity lubrication system in machining Ti-6Al-4V alloy
,” Tribol. Int.
, vol. 145
, 2020
, doi: .21.
R.
Uma
and P.
Dhavachelvan
, “Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits
,” Procedia Technol.
, vol. 6
, pp. 74
–81
, 2012
, doi: .22.
M. S.
Hiremath
and D. D.
Koppad
, “Low Power Circuits using Modified Gate Diffusion Input (GDI
),” IOSR J. VLSI Signal Process.
, vol. 4
, no. 5
, pp. 70
–76
, 2014
, doi: .23.
D.
Soni
and M. V
Shah
, “Review on Modified Gate Diffusion Input Technique
,” Int. Res. J. Eng. Technol.
, vol. 4
, no. 4
, pp. 874
–878
, 2017
.24.
V.
Foroutan
, M.
Taheri
, K.
Navi
, and A. A.
Mazreah
, “Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
,” Integr. VLSI J.
, vol. 47
, no. 1
, pp. 48
–61
, 2014
, doi: .
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