Analysis of delay and power consumption for a nine bit successive approximation type register analog to digital converter

In applications like industrial control and data acquisition, successive approximation register (SAR) analog to digital converter (ADC) is necessary. The low power consumption and small form factor make the SAR ADC to be applied in larger functions for getting high resolution. The sampling rate for SAR ADC is approximately 15 mega sample per second (MSPS) and the obtainable resolution is about 18 bits. There is no latency when SAR is used. Including high sampling rate SAR ADC is the most suitable type for data acquisition multiplexing. The basic design of this SAR will be combination of many components like switching controls, multiple digital to analog converter (DAC) array’s, which increases the area, delays and complexity. Due to comparator and offset cancellation we will lose data. To overcome these issues we have proposed the implementation of SAR ADC in an efficient way by using binary capacitor array, retiming and clock generator. If we are supposed to do frontend we will be using Xilinx. If we are supposed to do backend we will be using DSCH -micro wind. We expect to get an efficient SAR ADC model which will propose low complexity. SAR ADCs find applications which are using the sampling rates below 5 MSPS. Resolution given by SAR ADC lies between 8 to 16 bits. The basic design of this SAR will be combination of many components like switching controls, multiple DAC array’s, which increases the area, delays and complexity. Due to comparator and offset cancellation we will lose data. To overcome these issues we have proposed the implementation of SAR ADC in an efficient way by using binary capacitor array, retiming and clock generator.