Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNTFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNTFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. A low power enoder is used for reducing the overall power of the adder. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in Power Delay Product (PDP) by 28 % compared to all other previous works.

Topics
Digital circuits, Electrical properties and parameters, Field effect transistors, Chirality
1.
M.
 
Mukaidono
, “
Regular ternary logic functions ternary logic functions suitable for treating ambiguity,” (Feb
.
1986
).
Google Scholar
 
2.
P. C.
 
Balla
 and
A.
 
Antoniou
, “
Low power dissipation mos ternary logic family,” (Oct
 
1984
).
Google Scholar
 
3.
A.
 
Heung
 and
H. T.
 
Mouftah
, “
Depletion/enhancement cmos for a lower power family of three-valued logic circuits, circuits,” (Apr
 
1985
).
Google Scholar
 
4.
D. A.
 
Rich
, “
A survey of multivalued memories,” (Feb
.
1986
).
Google Scholar
 
5.
S. Z. K. P. T. N. Y.
 
Yasuda
,
Y.
 
Tokuda
 and
A.
 
Yoshida
, “
Realization of quaternary logic circuits by n-channel mos devices,” (Feb
.
1986
).
Google Scholar
 
6.
J.
 
Appenzeller
, “
Carbon nanotubes for high-performance electronics - progress and prospect,” (Feb
 
2008
).
Google Scholar
 
7.
K. N. R. F.
 
Mirzaee
 and
N.
 
Bagherzadeh
, “
High-efficient circuits for ternary addition
,” (
2014
).
Google Scholar
 
8.
Y. B. K. S.
 
Lin
 and
F.
 
Lombardi
, “
Cntfet-based design of ternary logic gates and arithmetic circuits,” (March
 
2011
).
Google Scholar
 
9.
S. G. K.
 
Sridharan
 and
V.
 
Pudi
, “
Efficient multiternary digit adder design in cntfet technology
,” (
2013
).
Google Scholar
 
10.
P.
 
Keshavarzian
 and
R.
 
Sarikhani
, “
A novel cntfet-based ternary full adder
,” (
2014
).
Google Scholar
 
11.
B.
 
Srinivasu
 and
K.
 
Sridharan
, “
Carbon nanotube fet-based low-delay and lowpower multi-digit adder designs
,” (
2016
).
Google Scholar
 
12.
C.
 
Vudadha
 and
M. B.
 
Srinivas
, “
High speed and power efficient ternary prefix adders using cnfets
,” (
2018
).
Google Scholar
 
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