The objective involves in construction of a Logical Built in Self Test using adaptive Multiple Input Signature Register designs that is mainly used for testing of the Integrated Circuits. One of the major issues is that, the complications in integrated circuit testing have been increased due to the emerging trends in the field of Very Large Scale Integration. This problem could be solved by increasing the usage of test equipment named Logical Built in Self Test shortly called as LBIST which works much well than any other test equipments. The logical BIST also has the advantage of performing a test that is in-built to the chip by means of an extra element that is present interior to the design. Test patterns for the operation are generated always by an inbuilt testing circuit as mentioned earlier. The output responses are determined with the help of a Multiple Input Signature Register, which is the most widely as the design is completely opposite to that of a Linear Feedback Shift Register design. The testing methodology is always invoked by a MISR by means of compressing multiple sequences of input bits as a single package named as signature of the design. The fault performance during a chip testing can be improved by means of a reconstructable Linear Feedback Shift Register which functions both to generate test patterns as well as to compress the responses required for logical Built in Self Testing. The QUCS simulator and SPICE tool is used to perform compilation of fast Multiple Input Signature Register design. Four structural representations namely Basic, Combined, Programmable and Advanced MISR are implemented and simulated using QUCS simulator and SPICE tool in 22nm technology. The output waveforms of the adaptive designs are obtained for different temperature variations ranging from 27°C to 107°C.
22nm 0.8V strained silicon based programmable MISR under various temperature ranges
P. Malini, T. Poovika, P. Shanmugavadivu, I. Rinisha Prem Priya, G. Naveen Balaji, Ravinder Nath Rajotiya, Amrish Kumar, Ganesh Mashette; 22nm 0.8V strained silicon based programmable MISR under various temperature ranges. AIP Conf. Proc. 20 March 2019; 2087 (1): 020004. https://doi.org/10.1063/1.5095220
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