Advanced concepts for TDDB reliability in conjunction with 3D stress

Time-Dependent Dielectric Breakdown (TDDB) in the Backend-of-Line (BEoL) stack has become one of the most important failure mechanisms for state-of-the art integrated circuits and threatens the long-term reliability of advanced semiconductor products. The continuous reduction in the BEoL feature sizes, resulting in continuously smaller spacing between interconnects, along with a slower pace in the reduction of the operational voltages, has led to significantly increased electrical fields. In addition, the introduction of low-k and ultra-low-k (ULK) materials has complicated the situation even more, since lifetimes for those materials are typically several decades shorter than for traditionally used $SiO2$⁠. While the reliability community has mostly adopted the square-root-E model for backend dielectric failure and has abandoned the more conservative linear-E-model, major questions about the true physical mechanism of dielectric failure, such as the role of Cu, still exist. Within the context of "More than Moore", the 3D IC integration approach promises to give a significant performance boost, power savings and cost reduction. However, globally and locally induced stresses, as well as additional complexities and interactions caused by the 3D process will influence the physical failure mechanisms for TDDB, leading to even shorter lifetimes. Possibly, lifetime data acquired with standard testing and extrapolation methods may overestimate the actual product lifetimes. Therefore, advanced concepts for the evaluation of BEoL "dielectric reliability" have to be developed. In this paper, we review the current status of TDDB testing, address the main issues and open questions, and finally we propose new concepts for a more realistic evaluation of the "dielectric reliability" within the context of mechanical stresses caused by 3D IC integration schemes.