Characterization of Strain Induced by PECVD Silicon Nitride Films in Transistor Channels

In order to reach high levels of transistor performance, it is desirable to increase electrical conductivity of the device. An efficient way to enhance carrier mobility in the conduction channel is to generate strain in the structure using process‐induced stress. To achieve that, stress engineering of the contact etch stop layer (CESL), an amorphous hydrogenated silicon nitride film deposited by plasma enhanced chemical vapour deposition on top of the metal oxide semiconductor assembly, is widely used since it is a low‐cost technique. Indeed, this film possesses an intrinsic stress that can be set from tensile $(σ = 1.6 GPa)$ to compressive $(σ = −3.0 GPa)$ depending on deposition conditions. From an electrical point of view, strain induced in the silicon channel can lead to an increase of carrier mobility as high as 8–10% which in turn increases $Ion/Ioff$ and decreases switching time of the transistor. Usually, strain induced in the channel is very low (0.1–0.3%), making quantitative measurements challenging. Moreover, stress transmission mechanisms are not fully understood at the nano‐metre scale. To evaluate stress transmission in the silicon channel, we used dark‐field electron holography characterization technique operating on both the Titan and Tecnai F20 transmission electron microscopes. Strain maps with nanometre spatial resolution, high sensitivity $(Δε≈10−3%)$ and large field of view $(400–500 nm2)$ have been obtained on CESL strained devices. In order to understand stress transfer mechanisms, we have analysed structures with varying spacing between patterns. The experimental results are compared to those obtained by 2‐D finite elements analysis simulation.