In very large scale integrated circuits (VLSIC’s), the materials and technologies, in particular deposition and patterning, play an ever increasing important role in multilevel metallizations. This is evident from the fact that the largest area on a VLSIC chip is occupied by multilevel metallizations. This is expected to be true also for chips in future VLSIC’s, usually referred to as ultra large scale integrated circuits (ULSIC’s). The chip sizes in VLSI and ULSI are not limited by device scaling; instead, they are governed by multilevel metallizations. The materials required for multilevel metallizations are in two categories: metals (conductors) and dielectrics (insulators). Both of these types of materials need to be chosen and used properly for successful multilevel metallizations. Associated technologies to use these materials are also essentially in two categories: deposition and patterning. A brief review of the most widely used materials and associated technologies, as well as their future directions, will be presented in this paper. It will also be shown that improved vacuum technologies are needed, which can significantly impact both the chemical vapor deposition (CVD) and physical vapor deposition (PVD) processes, and PVD can regain some of the territory lost to CVD.
Skip Nav Destination
Dissertation| April 20 1986
A. N. Saxena; Materials and technologies for multilevel metallizations in VLSI. AIP Conf. Proc. 20 April 1986; 138 (1): 281. https://doi.org/10.1063/1.35563
Download citation file:
Don't already have an account? Register
You could not be signed in. Please check your credentials and make sure you have an active account and try again.
Could not validate captcha. Please try again.