Jitter is a matter of great concern for high‐speed digital designers because of its ability to degrade the overall system performance. Designing a low‐jitter and wide‐band phase locked loop (PLL) system is of practical importance because of its application in high speed digital systems. This paper experimentally investigates a low‐jitter and wide‐band dual cascaded PLL system using a single crystal oscillator. The first PLL used in the system employs a voltage‐controlled crystal oscillator (VCXO) to eliminate the input jitter whereas the second PLL provides wide bandwidth. Field Programmable Gate Array (FPGA) is used to generate a jittered clock source which is then passed through the proposed system to achieve wide‐band and low‐jitter signal. Experimental results are presented to validate the proposed technique for different carrier frequencies.
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25 August 2011
IAENG TRANSACTIONS ON ENGINEERING TECHNOLOGIES VOLUME 6 ‐ SPECIAL EDITION OF THE WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE 2010
20–22 October 2010
San Francisco, CA, (USA)
Research Article|
August 25 2011
Experimental Investigation of Low‐Jitter and Wide‐Band Dual Cascaded PLL System
Ahmed Telba;
Ahmed Telba
King Saud University, College of Engineering, P.O. Box‐800, Department of Electrical Engineering, Riyadh, Saudi Arabia 11421
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Syed Manzoor Qasim
Syed Manzoor Qasim
King Saud University, College of Engineering, P.O. Box‐800, Department of Electrical Engineering, Riyadh, Saudi Arabia 11421
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AIP Conf. Proc. 1373, 59–69 (2011)
Citation
Ahmed Telba, Syed Manzoor Qasim; Experimental Investigation of Low‐Jitter and Wide‐Band Dual Cascaded PLL System. AIP Conf. Proc. 25 August 2011; 1373 (1): 59–69. https://doi.org/10.1063/1.3627194
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