Jitter is a matter of great concern for high‐speed digital designers because of its ability to degrade the overall system performance. Designing a low‐jitter and wide‐band phase locked loop (PLL) system is of practical importance because of its application in high speed digital systems. This paper experimentally investigates a low‐jitter and wide‐band dual cascaded PLL system using a single crystal oscillator. The first PLL used in the system employs a voltage‐controlled crystal oscillator (VCXO) to eliminate the input jitter whereas the second PLL provides wide bandwidth. Field Programmable Gate Array (FPGA) is used to generate a jittered clock source which is then passed through the proposed system to achieve wide‐band and low‐jitter signal. Experimental results are presented to validate the proposed technique for different carrier frequencies.

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