A Study of Flash Anneal in combination with the conventional RTA for DRAM application Available to Purchase

We have investigated the effects of FLA technique on the DRAM peripheral transistor improvements by integrating into the SDRTA (Source/Drain RTA) and ADD RTA (Add RTA after contact formation). FLA with conventional RTA was not effective because of SCE (Short Channel Effect) control. FLA only was effective to improve SCE and Iop, and especially more effective on technology shrink. By flash anneal (FLA), we tried to achieve better activation, lower series resistance and less dopant loss. For higher activation, the pre‐heat temperature of FLA was varied by 50 °C higher or lower than the desired base temperature. For lower resistance, the sidewall spacer thickness was reduced by 50 Å, 100 Å and 150 Å. For reducing dopant loss during the contact etch process, the deeper S/D Rp was used by increasing the S/D implant energy with an increased Rp by 150 Å, 200 Å and 250 Å. Results with FLA base show 13.4% improvement, and at the higher pre‐heat temperature, it can be improved to 16.9%. In conclusion, FLA can be one of the candidates for periperal transistor performance improvement of next generation DRAM device.