Circuits for four-bit digital/analog (D/A) and analog/digital (A/D) converters, suitable for the laboratory of an introductory electronics course, are provided. By placing variable resistors in the D/A circuit, students have some control over the step sizes in the conversion process. A component level A/D provides students an opportunity to directly observe the steps in the conversion process.

1.
For a discussion of these conversion processes, see, for example, P. Horowitz and W. Hill, The Art of Electronics, 2nd ed. (Cambridge UP, Cambridge, UK, 2001), 2nd ed.
2.
The students in this introductory course for nonphysics students have not had general physics nor any previous experience with circuits.
3.
See, for example, Ref. 1, p. 916.
4.
In this four-bit D/A conversion process, we use an op-amp in a summing circuit configuration. Currents passing through the input resistors add together at the summing junction and pass through the feedback resistor. The op-amp output voltage is $−Itot$$Rfeedback.$ In this case, we will apply voltages corresponding to either logic low or logic high to each of the input resistors and choose resistances that double in value stepwise. Thus, with inputs high, the current in adjacent resistors differ by a factor of 2 as do adjacent values in a binary counting system. If we think of a given set of inputs (some combination of logic lows and logic highs—0’s and 1’s) as corresponding to a binary number, each time we increase the input count by one, the current increases one increment, and the output voltage decreases one increment. If we proceed in a counting sequence 0000, 0001, 0010,…, each unit increase in the input count results in a corresponding step down in the analog output voltage. Taken as a whole, the resulting analog output has the appearance of a staircase if the time at each count is the same.
5.
Open-collector TTL gates do not have the typical totem-pole output stage. Instead of a series sequence from power to ground of a resistor, an $npn$ transistor, a diode, and an $npn$ transistor with its emitter connected to ground, only the transistor with grounded emitter is maintained. The output is taken from the collector of this transistor; such circuits normally require an external pull-up resistor for transitions to logic high. Tri-state refers to the possible output states of a gate. Normally, logic gates have two output states, logic low, and logic high. With tri-state gates, the output transistors (which normally provide a connection allowing the output to be either high or low) can be disabled so that the output is only connected to either ground or power via a very high impedance, or Hi-Z, a third output condition. In this circuit, the buffers pass the clock signal when enabled and are in Hi-Z mode otherwise.
6.
The input impedance to the comparator is sufficiently large that we need not worry about loading the divider.
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